Residential College | false |
Status | 已發表Published |
A digital SC converter with high efficiency and low voltage ripple | |
Jiang J.1; Ki W.-H.1; Lu Y.2 | |
2018-02-20 | |
Conference Name | 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Source Publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
Volume | 2018-January |
Pages | 289-290 |
Conference Date | JAN 22-25, 2018 |
Conference Place | Jeju, SOUTH KOREA |
Abstract | A switched-capacitor DC-DC converter with a low output voltage ripple and high efficiency is presented in this summary. To achieve a wide input and output voltage range, a 3-clock-phase operation is proposed to achieve 6 voltage conversion ratios (VCRs) with only two discrete flying capacitors. A digital ripple reduction scheme is utilized to achieve up to four times reduction in output voltage ripple. The digital design also improves the design flexibility. The converter can deliver a 250mW maximum power to a wide output range of 0.5 V to 3 V with an input range of 1.6 V to 3.3 V, and achieves a peak efficiency of 91%. |
DOI | 10.1109/ASPDAC.2018.8297324 |
URL | View the original |
Language | 英語English |
WOS ID | WOS:000426987100051 |
Scopus ID | 2-s2.0-85045326648 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | University of Macau |
Affiliation | 1.Hong Kong University of Science and Technology 2.Universidade de Macau |
Recommended Citation GB/T 7714 | Jiang J.,Ki W.-H.,Lu Y.. A digital SC converter with high efficiency and low voltage ripple[C], 2018, 289-290. |
APA | Jiang J.., Ki W.-H.., & Lu Y. (2018). A digital SC converter with high efficiency and low voltage ripple. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2018-January, 289-290. |
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