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A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation
Wang B.2; Law M.K.3; Mohamad S.2; Bermak A.2
2016-03-07
Conference Name21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Source PublicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016
Pages7-8
Conference DateJAN 25-28, 2016
Conference PlaceMacao, PEOPLES R CHINA
Abstract

A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18μm CMOS, the 0.12mm ADC consumes 2.16μW at a conversion speed of 85S/s, 15.3b resolution and-2/1.5LSB INL.

KeywordDual-feedback Σs Modulator Incremental Delta-sigma Adc Integrator Multiplexing Low Power Adc
DOI10.1109/ASPDAC.2016.7427975
URLView the original
Indexed BySCIE
WOS Research AreaAutomation & Control Systems ; Engineering
WOS SubjectAutomation & Control Systems ; Engineering, Electrical & Electronic
WOS IDWOS:000384642200004
Scopus ID2-s2.0-84996636567
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Citation statistics
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Affiliation1.Hamad Bin Khalifa University
2.Hong Kong University of Science and Technology
3.Universidade de Macau
Recommended Citation
GB/T 7714
Wang B.,Law M.K.,Mohamad S.,et al. A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation[C], 2016, 7-8.
APA Wang B.., Law M.K.., Mohamad S.., & Bermak A. (2016). A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 25-28-January-2016, 7-8.
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