An area-efficient low-power fully integrated output-capacitorless low-dropout regulator (OCL-LDO) is presented in this paper. The three-stage OCL-LDO utilizes an embedded differentiator-based active zero compensation technique together with adaptive biasing. The proposed active zero compensation helps enhance the unity-gain bandwidth (UGB) of the regulator with very small silicon area and almost no extra current consumption. The UGB is therefore able to be maintained above 2.5 MHz even at a measured quiescent current of mere 1.6 mu A. Adaptive bias is employed to further stabilize the circuit and extend the bandwidth extension as well as enhance the transient response. The chip area is 0.0021 mm(2) with maximum load capability of 25 mA, which leads to a maximum current density of 11.9 A/mm(2). The measured voltage spikes are below 40 mV for full-load transient responses, and the response time is about 1.2 ns. The voltage spikes of line transient responses are only 4 mV at full load. The measured full-load power-supply rejection is better than -44 dB up to 104) kHz.