| Residential College | false |
| Status | 已發表Published |
| A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing | |
Yaozhong Ou ; Wei-Han Yu ; Ka-Fai Un; Chi-Hang Chan; Yan Zhu
| |
| 2024-03 | |
| Source Publication | IEEE Transactions on Circuits and Systems II: Express Briefs
 |
| ISSN | 1549-7747 |
| URL | View the original |
| Indexed By | SCIE |
| Publisher | IEEE |
| Document Type | Journal article |
| Collection | INSTITUTE OF MICROELECTRONICS |
| Affiliation | University of Macau |
| First Author Affilication | University of Macau |
| Recommended Citation GB/T 7714 | Yaozhong Ou,Wei-Han Yu,Ka-Fai Un,et al. A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024. |
| APA | Yaozhong Ou., Wei-Han Yu., Ka-Fai Un., Chi-Hang Chan., & Yan Zhu (2024). A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. IEEE Transactions on Circuits and Systems II: Express Briefs. |
| MLA | Yaozhong Ou,et al."A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing".IEEE Transactions on Circuits and Systems II: Express Briefs (2024). |
| Files in This Item: | There are no files associated with this item. | |||||
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