This article proposes a novel eight-phase selfbias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors (C_P) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18-µm CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88×. In addition, with the four C_P serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of >3.5× can be maintained with a PEH input voltage from 0.78 to 4.9 V.