A Low-Dropout Regulator (LDO) with low quiescent current is proposed. The LDO uses a variable capacitance tracking zero compensation to enhance the stability within a wide load current range. Furthermore, it utilizes adaptive biasing current for a low quiescent current at the steady-state, while a transient enhancement circuit to improve transient response. Designed with a 65-nm CMOS process, the proposed LDO consumes a 5-nA quiescent current and supports a maximum 50-mA load current. The simulated output undershoot is 137 mV when the LDO has a load current step from 0 to 50 mA, with a 0.4-ns edge time.