In high-performance computing applications, a fast-Transient and high-efficiency buck converter is crucial. It is desirable to achieve one-cycle charge balance (OCB) that minimizes the undershoot/overshoot (US/OS) voltage and the recovery time (tUS/tOS), under a rapid load current change δ lLOAD). Fig. 1 explains how to achieve OCB for a buck converter. It detects an lLOAD step-up at t0 and turns on the high-side switch instantly, raising the inductor LO) current lL that intersects lLOAD at t1 (the output capacitor CO 's current lCO=0). After that, VOUT begins to recover to the reference voltage VREF, The high-side switch turns off at t22 and hence 1L ramps down, crossing lLOAD at t33. Clearly, if we detect t0 and t1 accurately, t2 can be derived from eq. (1)-(2), ensuring the areas Q1=Q2 and thus OCB. Similarly, we can achieve OCB under an ILOAD step-down if t2 is obtained from eq. (3)-(4). This scheme is also applicable to a low-slew-rate δ lLOAD, where the resultant Q2 is slightly larger than Q1 (almost OCB). Hysteretic control [1]-[3] can realize fast t0 detection, but it fails to detect t1 for OCB. [4]-[5] used capacitor current sensor (CCS) for precise t1 detection. However, the mismatches on Co, equivalent series resistance ESR, and inductance ESL undermine the detecting accuracy. Fig. 1 compares the detected signal VSENS with lCO under ESR mismatch, where the zero-crossing point t1 detection lags behind. Therefore, the CCS schemes should calibrate three parameters CO, ESR, and ESL, assisted by high-Accuracy inductor current sensors and hence complexing the design.