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22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer
Cao, Yuefeng1; Zhang, Minglei1; Zhu, Yan1; Martins, R. P.1,2; Chan, Chi Hang1
2024
Conference Name2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages388-390
Conference Date18 February 2024through 22 February 2024
Conference PlaceSan Francisco
PublisherInstitute of Electrical and Electronics Engineers Inc.
Abstract

Direct RF sampling relieves the analog front-end design and delivers high system flexibility. In >10GS/s >10b ADCs, time-interleaving (TI) is inescapable [1-3], while the number of channels and their front-end components should be minimized to achieve low power and adequate linearity for a wideband input. Moreover, the complexity and hardware cost associated with background calibrations of TI impairments should be minimized. However, prior calibrations face challenges to be comprehensive, which either confine the applicable input [1-3] or the accuracy [4,5]. This work presents a global dither-injection-facilitated comprehensive calibration of TI errors (CCTI), which features an inherent input-independent characteristic like the analog calibration of [5], but more comprehensively corrects all sources of skew. The CCTI is instantiated in a 12GS/s 12b ADC in 28nm, which is only aggregated by 4 TI channels (CHs), enabling a single input buffer (IBF) with direct sampling TI front-end for high energy efficiency. The IBF works under a 1.2V supply voltage headroom and is linearized by a self-adaptive currentcompensation cell (SACC-cell), accommodating >65dB SFDR over the Nyquist bandwidth. The ADC dissipates 179.8mW power and measures 54.1dB Nyquist SNDR, yielding 36.2fJ/conv.-step FoMW and 159.3dB FoMS.

DOI10.1109/ISSCC49657.2024.10454350
URLView the original
Language英語English
Scopus ID2-s2.0-85188075745
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Citation statistics
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau, Macao
2.University of Lisboa, Instituto Superior Tecnico, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Cao, Yuefeng,Zhang, Minglei,Zhu, Yan,et al. 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 388-390.
APA Cao, Yuefeng., Zhang, Minglei., Zhu, Yan., Martins, R. P.., & Chan, Chi Hang (2024). 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 388-390.
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