We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63% positive prediction (Pr) using the MIT-BIH Arrhythmia database. A chip prototype is also implemented in a standard 0.18-μm CMOS process. Synthesized with a customized subthreshold digital library for minimum energy operation, the proposed QRS detector occupies an active area of 0.13 mm and consumes merely 93nW.