This brief presents a 1-A fully-integrated switching LDO for digital loads. By using 4-phase 200-MHz pulse-width modulation (PWM), it can significantly reduce the output ripple and allow using a smaller output capacitor. Distinctive from the prior dual-loop structure, we adopt a single feedback loop with a wide bandwidth error amplifier (EA) using a quasi-Type-III compensation to improve the dynamic voltage scaling (DVS) rate and to reduce the transient recovery time. Meanwhile, compared with the prior stacked power transistor architecture, the single-PMOS with auxiliary constant current (ACC) control can reduce by 4-fold the power transistor size, and decreases the driver current by at least 2.5 times. Fabricated in 28-nm bulk CMOS, the proposed LDO measures a 1-A load capability with a 40-mV dropout voltage. Moreover, the measured load regulation is 2.2 mV/A, and the line regulation is 1.8 mV/V. In addition, the regulator obtains a fast DVS speed of 4V/μs and a fast load transient recovery time of <50ns.