Scaling down supply voltage (VDD) to sub-O.4V is tremendously attractive for the internet-of-things (loT) applications, which offers a great benefit to extending the lifetime of loT devices or enabling batteryless operation [1]. Furthermore, tailoring an ultra-low-voltage (ULV) phase-locked loop (PLL) to simultaneously lower power consumption, integrated jitter, and reference (REF) spur is highly desirable, especially for loT radios. Several LC-based ULV-PLLs have been reported, e.g., all-digital PLL (AD-PLL) [1], charge-pump-based PLL (CP-PLL) [2], and XOR-gate-based PLL (XOR-PLL) [3]. Yet, the limited resolution of the time-to-digital converter in the AD-PLL, and the poor CP current noise in the CP-PLL, noticeably degrade the in-band phase noise (PN) and integrated jitter. Besides, the poor CP current mismatch in a CP-PLL and the type-l loop feature of an XOR-PLL cause high reference spur levels. Alternatively, due to its inherently low in-band PN and relaxed-CP-design challenges, a sub-sampling PLL (SS-PLL) [4] can alleviate the above issues, and recently a 0.65V low-voltage (LV) SS-PLL was reported [5]. However, when further squeezing the SS-PLL VDD down to sub-O.4V, several new issues arise, such as a limited tuning range of the voltage-controlled oscillator (VCO), a limited voltage headroom of the VCO isolation buffer (ISO-BUF), and a large on-resistance of the sub-sampling phase detector (SSPD), resulting in the degradation of in-band PN and reference spur.