High-speed pipelined ADCs rely on fast and accurate residue amplification which often necessitates calibration, thus suffering from potential convergence issues, extra area/power overhead, and higher test costs. The state-of-the-art open-loop (OL) residue amplifiers (RAs) accommodate short amplification time [1] with decent calibration-free gain variation over PVT [2], reaching higher performance is challenging due to the absence of closed loop (CL) assistance. A ring-amp in a CL topology is a promising alternative, showing a 2 times amplification within 420ps in a 16nm process [3]. Its ring-able nature, however, imposes a precise dead-zone (DZ) control for optimum performance over PVT in high-speed applications, which in turn loses the calibration-free characteristic common in CL architectures. This work presents a calibration-free critically damped ring amplifier (CDRA) exploited in a time-domain (TD) ADC assisted pipelined ADC. The CDRAs retain 4times/8times PVT-stable amplification within 130ps, facilitating a single-channel 12b 2GS/s ADC in 28nm CMOS with 60.4dB SNDR at Nyquist.