Bluetooth Low Energy (BLE) System on Chip (SoC) demands ultra-low-power circuits to extend battery life or even achieve a battery-free goal. When harvesting the ambient energy (such as solar and thermal) without a battery, only a low range of supply output voltage (0.2-0.5V) can be provided. Typically, in the receiver-end, two 8-bit 1MS/s voltage domain analog-to-digital converters (ADCs) are utilized to quantize the phase information between I/Q signals for Gaussian Frequency-Shift Keying (GFSK) modulation [1] [2]. Nevertheless, under such a low supply voltage, designing an 8b ADC is very challenging, which inevitably limits the overall supply voltage of the system or calls for a low-efficiency supply boosting circuit. Rather than this classical solution, those two 8b ADC can be replaced by a single 4b phase ADC [1]. It quantifies the phase between I/Q signals directly and therefore allows lower resolution and hardware saving [1] [3] -[5]. However, the energy efficiency of the phase ADC in literature is an order poor than the voltage domain ADCs (FoMwalden in PJ/conv. range). In [1], the phase ADC uses a full-flash structure that quantizes the phase by detecting the zero crossing of the input signal, where its linear current combiner and comparators consume significant static power. Another phase ADC uses an IQ-assisted binary-search algorithm, which eliminates the need for the linear combiner and reduces the number of comparisons from 2N-1 in [1] to N+1 for an N-bit phase ADC [4]. However, the structure needs a power-hungry T&H. Recently, a phase ADC based on the time-domain operation is shown in [5] with only dynamic power. Unfortunately, the design needs additional buffers and a phase-lock-loop to ensure a proper function, thus still in high power.