Pipeline analog-to-digital converters (ADCs), which dominated high-speed and high-resolution applications, suffered from weak improvement in power efficiency. To address such a problem, this brief presents a 14-bit split-pipeline opamp-sharing ADC, with background calibration that optimizes duty-cycle ratio and amplifier power consumption in the shared opamp. Based on the interstage gain (that includes settling) error estimated by the split ADC calibration engine, the clock duty-cycle ratio and the bias current are adjusted to achieve better dynamic settling and resolution trade-offs. Operating at 100 MS/s with a 9-MHz input signal, the ADC achieves 46.5 dB of signal-to-noise-and-distortion ratio (SNDR) and 59.6 dB of spurious-free dynamic range (SFDR) before calibration, and after calibration, it improves to 71.7 dB of SNDR and 84.4 dB of SFDR, respectively. The ADC maintains an SNDR over 68.5 dB within the full Nyquist bandwidth consuming 32 mW of power, which yields a Walden figure-of-merit (FoM) of 147.2 fJ/conversion-step and a Schreier FoM of 160.4 dB.