This paper will first analyze the output phase-skew effects with embedding the practical sample-and-hold nature in high-speed, time-interleaved sampled-data systems. Closed-formed expressions will be presented with the verification by numerical computer simulations. Special design techniques and layout issues for reducing both the random process and the systematic mismatches will be presented through a real application of a low phase-skew clock generation circuit that is used for a very high-frequency SC multirate filter with 320 MHz output sampling rate. Measurement results (skew noise tones <-72dBc) will further verify the proposed techniques.