In very high-speed pipelined analog-to-digital converters (ADC's), stabilizing the reference voltage with large off-chip capacitor is no longer appropriate, as such capacitor will resonate with the effective inductance of the bondwire. However, creating a stable and high-speed reference internally not only consumes a lot of power and area, but also makes the reference highly sensitive to internal noises. This paper presents the process of analytical modeling and the characterization of the significant noise sources, which comprisse: 1) Sample-variant error voltage due to dynamic loading fluctuations, 2) Static offset voltage due to finite precision of bandgap reference, mismatches in resistor ladder and driving buffer, 3) Random noise modulation. The resulting effects are discussed in terms of the key parameters, ENOB and SFDR. The effectiveness of the modeling methods and deduced equations are also verified either by behavioral or circuit simulations which are particularly helpful in the determination of circuit-level specifications and in compromising different design trade-offs.