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A digital background nonlinearity calibration algorithm for pipelined ADCs
Fei Y.; Sin S.-W.; U S.-P.; Martins R.P.
2010-12-20
Conference Name2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)
Source PublicationPrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Pages115-118
Conference Date22-24 Sept. 2010
Conference PlaceShanghai, China
Abstract

This paper presents a new digital background calibration algorithm for pipelined analog-to-digital converters (ADCs). Background calibration can extract calibration data without interrupting ADCs normal conversion operation. Digital calibration can relax the design difficulty of analog circuits of ADCs, and gains the improvement of technology scaled down. This algorithm provides a method to effectively estimate the nonlinearity of opamp, and calibrates it in digital domain without any additional analog circuit. Simulation results show that the ENOB can be improved from 6.3b to 10.67b by the proposed algorithm.

DOI10.1109/PRIMEASIA.2010.5604949
URLView the original
Language英語English
Scopus ID2-s2.0-78650136962
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Citation statistics
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
AffiliationUniversidade de Macau
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Fei Y.,Sin S.-W.,U S.-P.,et al. A digital background nonlinearity calibration algorithm for pipelined ADCs[C], 2010, 115-118.
APA Fei Y.., Sin S.-W.., U S.-P.., & Martins R.P. (2010). A digital background nonlinearity calibration algorithm for pipelined ADCs. PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 115-118.
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