This paper presents a background-calibration technique of timing skew for time-interleaved analog-to-digital converters (TIADCs). Without any kind of additional calibration signals, the timing skew between any two adjacent interleaved channels is detected by the capacitive charge pumps, and minimized by the digitally controlled delay elements (DCDEs). The calibration behaviors are analyzed and verified on transistor-level simulations. An 8-bit 4-channel TIADC is used as an example for demonstration. The simulation results show that the proposed technique can improve the SNDR from 35.1 dB to 49.6 dB at Nyquist input frequency as the extreme case. © 2011 IEEE.