In the design of green circuit, the most effective way for low power is to reduce the supply voltage. However, the accuracy of pipelined ADC is limited by the residue amplification. The inaccurate residue amplification is much worse in an ultra-low voltage condition because of the lack of the headroom for transistors in the opamp. This paper describes a new background calibration technique for the pipelined ADCs designed in the ultra-low supply voltage. Based on the Least Mean Square (LMS) algorithm and the digital nonlinear interpolation, the proposed calibration technique corrects the interstage gain error. It is a fully digital approach and only needs very little analog modifications, which increases the design flexibility and reduces the production cycle. © 2013 IEEE.