This work proposes a hybrid DC-DC converter using a multipath switched-capacitor-inductor (MPSCI) topology. Assisted by switched-capacitor branches, it features voltage-conversion range extension and inductor power loss reduction, and hence improving the conversion efficiency. Implemented in a 180-nm CMOS process, the proposed converter can regulate an output voltage of 1.8 similar to 3.3V from a 5-V input bus voltage using a 4.7 mu H inductor (DCR = 240m Omega) at a switching frequency of 800 kHz. It achieves a peak conversion efficiency of 93.7% when delivering an output current of 1 A. Under a maximum loading of 3 A, this design still attains an efficiency of up to 85.8%. Furthermore, in contrast to the existing dual-path and conventional buck topologies, the proposed converter realizes an inductor loss reduction up to 3.3 and 5.4 times, respectively, at the maximum loading conditions.