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A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF with 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
Yaohua Zhao1; Pui-In Mak1; Rui P. Martins1; Franco Maloberti1,2
2015-09-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN00189200
Volume50Issue:9Pages:1988-2001
Abstract

This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-loop unity-gain buffers; both are friendlier to technology downscaling than most conventional Biquads that use high-gain amplifiers and closed-loop negative feedback. Complex-pole pairs with independent Q factors are recursively realized in one clock period, while ensuring low crosstalk effect between the formations of each pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-recycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occupies a die size of only 0.02 mm and exhibits 20x bandwidth tunability (0.5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/√Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-of-merit which are favorably comparable with the recent art. The 1 dB compression point (P dB) conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end gain.

Keyword1 Db Compression Point ({p1Db) Butterworth Channel Selection Clock Generator Clock-rate-defined Bandwidth (Bw) Cmos Die Area Figure-of-merit (Fom) Long-term Evolution (Lte) Low-pass Filter (Lpf) Operational Transconductance Amplifier (Ota) Recycling Switched Capacitor (Sc) Wireless Radios
DOI10.1109/JSSC.2015.2427334
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000360889300003
Scopus ID2-s2.0-85027935034
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Citation statistics
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)
INSTITUTE OF MICROELECTRONICS
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China
2.Instituto Superior Técnico, Universidade de Lisboa, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Yaohua Zhao,Pui-In Mak,Rui P. Martins,et al. A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF with 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad[J]. IEEE Journal of Solid-State Circuits, 2015, 50(9), 1988-2001.
APA Yaohua Zhao., Pui-In Mak., Rui P. Martins., & Franco Maloberti (2015). A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF with 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad. IEEE Journal of Solid-State Circuits, 50(9), 1988-2001.
MLA Yaohua Zhao,et al."A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF with 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad".IEEE Journal of Solid-State Circuits 50.9(2015):1988-2001.
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