Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques

doi:10.1109/ASPDAC.2016.7427979

UM > THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)

Residential College	false
Status	已發表Published
	Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques
	Ming-Zhong Li 1; Chio-In Ieong 1; Man-Kay Law1 ; Pui-In Mak1 ; Mang-I Vai1 ; Sio-Hang Pun1 ; Rui P. Martins1,2
	2016-03-07
Conference Name	21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Source Publication	2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Volume	25-28 Jan. 2016
Pages	15-16
Conference Date	JAN 25-28, 2016
Conference Place	Macau, China
Abstract	This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-μm CMOS technology, while one of them achieved the minimum energy/tap (0.0234 pJ) and 0.365 Figure-of-Merit (FoM) at 100 kHz, 0.31 V.
DOI	10.1109/ASPDAC.2016.7427979
URL	View the original
Indexed By	SCIE
Language	英語English
WOS Research Area	Automation & Control Systems ; Engineering
WOS Subject	Automation & Control Systems ; Engineering, Electrical & Electronic
WOS ID	WOS:000384642200008
Scopus ID	2-s2.0-84997017370
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding Author	Ming-Zhong Li
Affiliation	1.State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China 2.On leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal
First Author Affilication	Faculty of Science and Technology
Corresponding Author Affilication	Faculty of Science and Technology
Recommended Citation GB/T 7714	Ming-Zhong Li,Chio-In Ieong,Man-Kay Law,et al. Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques[C], 2016, 15-16.
APA	Ming-Zhong Li., Chio-In Ieong., Man-Kay Law., Pui-In Mak., Mang-I Vai., Sio-Hang Pun., & Rui P. Martins (2016). Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 Jan. 2016, 15-16.

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