This paper proposes a dual-layer patterned floating shield (DL-PFS) technique for Silicon-based on-chip spiral inductors. By optimally utilizing the two lowest metal layer strips to shield the inductor from the substrate, electromagnetic (EM) simulations show 40% improvement of the Q factor when compared with the conventional approach. Designed and simulated in 0.13-μm CMOS, the DL-PFS inductor in a class-B VCO achieves 6.6-dB lower phase noise, and 34% power savings. The VCO also exhibits 9.7-to-10.93 GHz tunability, and -123-dBc/Hz phase noise at a 3 MHz offset. The power consumption is 1.64 mW at 0.6 V, leading to a state-of-the-art FoM of 190.5 dBc/Hz.