An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology

doi:10.1109/ESSCIRC.2016.7598331

UM > Faculty of Science and Technology > DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

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	An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology
	Dante Gabriel Muratore 1; Alper Akdikmen 1; Edoardo Bonizzoni 1; Franco Maloberti 1; U-Fat Chio 2; Sai-Weng Sin2 ; Rui Paulo Martins 2,3
	2016
Conference Name	46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC)
Source Publication	ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
Pages	421-424
Conference Date	12-15 Sept. 2016
Conference Place	Lausanne, Switzerland
Abstract	This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 x 220 µm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.
DOI	10.1109/ESSCIRC.2016.7598331
URL	View the original
Indexed By	SCIE
Language	英語English
WOS Research Area	Engineering
WOS Subject	Engineering, Electrical & Electronic
WOS ID	WOS:000386656300102
Scopus ID	2-s2.0-84994474437
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS
Affiliation	1.Department of Electrical, Computer and Biomedical Engineering University of Pavia, Pavia, Italy 2.State-Key Laboratory of Analog and Mixed Signal VLSI University of Macau, Macau, China 3.on leave from Instituto Superior Tecnico ´ Universidade de Lisboa, Lisbon, Portugal
Recommended Citation GB/T 7714	Dante Gabriel Muratore,Alper Akdikmen,Edoardo Bonizzoni,et al. An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology[C], 2016, 421-424.
APA	Dante Gabriel Muratore., Alper Akdikmen., Edoardo Bonizzoni., Franco Maloberti., U-Fat Chio., Sai-Weng Sin., & Rui Paulo Martins (2016). An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 421-424.

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