This paper presents a 5-bit 2GS/s binary-search ADC. The proposed architecture prevents the use of a decoder to avoid the path delay racing between control signals and clock phases; thence the bit latency reduces to 1 single comparator delay only. We also propose a dynamic charge-steering comparator to quantize each bit quickly. Besides, we present well-balanced 1-of-N-to-Binary encoders to transform the output code with low power. This ADC consumes 3.9mW at 2GS/s in 65nm CMOS. It achieves a SNDR of 28 dB at Nyquist rate resulting in a FoM of 95 fJ/conv.-step.