This paper presents an analysis based on the impulse sensitivity function to precisely characterize and estimate the jitter caused by the common-mode interference (CMI). Unlike the conventional common-mode rejection ratio concept, the proposed method considers the CMI jitter in a transient rather than in an ac perspective. Inspired by the analytical results, we propose a clock receiver circuit (CRC) based on the self-bias amplifier topology. The accuracy of the analysis and the efficiency of the proposed CRC are verified both in simulations and measurements. A 1-GS/s ADC was fabricated in 65-nm CMOS containing simultaneously three CRCs, including an inverter-chain, a differential amplifier and the proposed structure, serving as the sampling clock. Both simulation and measurement results show a good agreement with the presented analysis. The proposed CRC achieves a 30-fs jitter with a 620- μW power at 1.2 V supply. With a similar CMI rejection and random jitter performance, the proposed CRC exhibits a 20-fold power reduction when compared with the state-of-art designs.